This is a scanned image of an actual 4-inch wafer (ca. 1990)
containing 100s of static RAM (SRAM) dice.  If one looks
carefully, one can see each die contains 2 banks of SRAM 
cells.  This technology used a 4-transistor CMOS cell for 
lower power and higher speed.

Note:  DRAM cells, such as that shown in the Am1101A die,
use only a single transistor per bit.  Thus, for any given
memory and process gneration, a DRAM chip had 4x the amount
of bit storage as a comparable SRAM.  For example, in 1988,
a 64-Kbit SRAM became available at the same time as a 256K
DRAM chip.  SRAMs are used for speed (up to 4x or more
faster), while DRAMs are for density/capacity (4x denser).

Wafers themselves have grown from an original 1-inch 
diameter, through 2 inches (1960s), 3 inches (1974), 4
inches (1985), 5 inches (1988), 6 inches (1994), 8 inches
(1998), and now 12 inches (300mm).

Attendantly, the value of a processed wafer (full of chips)
has grown exponentially from ~$1000 to $100,000 or more.